Integer Fetch Decode
نویسندگان
چکیده
Instruction scheduling is essential for the eecient operation of today's and to-morrow's processors. It can be stated easily and declaratively as a logic program. Consistency techniques embedded in logic programming enable the eecient solution of this problem. This paper describes an instruction scheduling program for the Motorola 88100 RISC processor, which minimizes the number of pipeline stalls. The scheduler is written in the constraint logic programming language ARISTO and uses a declarative model of the processor to generate an optimal schedule. The model uses lists of domain variables to represent the pipeline stages and describes the dependencies between instructions by constraints in order to ensure correct scheduling. Although optimal instruction scheduling is NP-complete, the scheduler can be applied to real programs because of the speed gained through consistency techniques.
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